Semiconductor Engineering

Adaptive RISC-V Cache Architecture for Near-Memory Extensions (Politecnico di Torino, EPFL)

A new technical paper titled “ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions” was published by researchers at Politecnico di Torino and EPFL. Abstract “Modern data-driven ...
TechRepublic

Cache-Only Memory Architecture

A Cache-Only Memory Architecture design (COMA) may be a sort of Cache-Coherent Non-Uniform Memory Access (CC- NUMA) design. not like in a very typical CC-NUMA design, in a COMA, each shared-memory ...
Semiconductor Engineering

An Energy-Efficient DRAM Cache Architecture for Mobile Platforms With PCM-Based Main Memory

“A long battery life is a first-class design objective for mobile devices, and main memory accounts for a major portion of total energy consumption. Moreover, the energy consumption from memory is ...
EDN

Memory models for embedded multicore SoCs, Part 1 – Memory architecture

Editor's Note: Multicore architectures find use across a diverse range of applications thanks to their performance and efficiency. By combining several general-purpose MCU cores — or MCU cores and ...
Nature

Data Prefetching Techniques in Computer Architecture

Data prefetching has emerged as a critical approach to mitigate the performance bottlenecks imposed by memory access latencies in modern computer architectures. By predicting the data likely to be ...
EDN

Memory Hierarchy Design – Part 1. Basics of Memory Hierarchies

Editor’s Note: Demand for increasing functionality and performance in systems designs continues to drive the need for more memory even as hardware engineers balance the dynamics of system capability, ...